Lithography tools used in the manufacture of integrated circuits have been around for some time. Such tools have proven extremely effective in the precise manufacturing and formation of very small details in the product. In most lithography tools, a circuit image is written on a substrate by transferring a pattern via a light beam. For example, the lithography tool may include a light source that projects a circuit image through a reticle and onto a silicon wafer coated with photoresist. The exposed photoresist typically forms a pattern that masks the layers of the wafer during subsequent processing steps, as for example deposition and/or etching. As is generally well known, materials are deposited onto the layers of the wafer during deposition and materials are selectively removed from the layers of the wafer during etching.
The measurement of overlay between successive patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it. Presently, overlay measurements are performed via targets that are printed together with layers of the wafer. The most commonly used overlay target pattern is the “Box-in-Box” target, which includes a pair of concentric squares (or boxes) that are formed on successive layers of the wafer. The overlay error is generally determined by comparing the position of one square relative to the other square. This may be accomplished with an overlay metrology tool that measures the relative displacement between the two squares.
To facilitate discussion, FIG. 1 is a top view of a typical “Box-in-Box” target 2. As shown, the target 2 includes an inner box 4 disposed within an open-centered outer box 6. The inner box 4 is printed on the top layer of the wafer while the outer box 6 is printed on the layer directly below the top layer of the wafer. As is generally well known, the overlay error between the two boxes, along the x-axis for example, is determined by calculating the locations of the edges of lines c1 and c2 of the outer box 6, and the edge locations of the lines c3 and c4 of the inner box 4, and then comparing the average separation between lines c1 and c3 with the average separation between lines c2 and c4. Half of the difference between the average separations c1&c3 and c2&c4 is the overlay error (along the x-axis) at that point. Thus, if the average spacing between lines c1 and c3 is the same as the average spacing between lines c2 and c4, the corresponding overlay error tends to be zero. Although not described, the overlay error between the two boxes along the y-axis may also be determined using the above technique.
Most overlay measurements are performed immediately after the photoresist is developed, i.e., the photoresist is developed away in the area where it was exposed to the light thus leaving the overlay pattern in the photoresist. In some cases, the overlay measurements are used to correct the process in order to keep the overlay errors within desired limits. For example, the overlay measurements may be fed into an analysis routine that calculates correctables and other statistics, which are used by the operator and/or the lithography tool to get the tool better aligned thus allowing wafer processing to proceed within desired limits. If the overlay error is too great, the analysis results may indicate that the wafer needs to be reworked, i.e., strip or remove the resist and start over on that layer. Reworking is typically expensive and undesirable, but it is better than scrapping the wafer all together. Overlay measurements can also be performed after process steps such as etch, when no photoresist is present. In this case, reworking is not possible, but the added information aids in the finer tuning of the overall process.
A typical semiconductor process includes wafer processing by lot. A lot is a group of typically 25 wafers which are processed together. Each wafer in the lot is comprised of many exposure fields from the lithography processing tools (e.g. steppers, scanners, etc.). Within each exposure field can be typically 1 to many die. A die is the functional unit which eventually becomes a single chip. On product wafers, overlay metrology marks are typically placed in the scribeline area (for example in the 4 corners of the field). This is a region that is typically free of circuitry around the perimeter of the exposure field (and outside the die). Sometimes overlay targets are placed in the streets, which are regions between the die but not at the perimeter of the field. It is fairly rare for overlay targets to be placed on product wafers within the prime die areas, as this area is critically needed for circuitry. Engineering and characterization wafers (not production wafers), however, typically have many overlay targets throughout the center of the field where no such limitations are involved. Because of the spatial separation between the “scribe-line” metrology marks and the prime die circuitry, there occur discrepancies between what is measured and what needs to be optimized on product wafers. Advances in both the scribe-line metrology marks and in their interpretation are required.
Unfortunately, the lithography tool's optical characteristics have a strong influence on overlay and critical dimension performance when patterning advanced design rule integrated circuits. Of particular importance are the optical aberrations of the lithographic lens system. Many examples exist today of methods used to quantitatively measure these optical aberrations. Three examples of these, each based on slightly different physical principles are the Litel reticle concept described in, “In Situ Measurement of Lens Aberrations”, N. R. Farrar, Hewlet-Packard Co.; A. H. Smith, Litel Instruments; D. R. Busath, KLA-Tencor Corp. [4000-03], March 2000, Proceedings of SPIE Vol. 4000, Optical Microlithography XIII; the Artemis concept described in SPIE vol. 3679 (1999) p. 77-86 “Novel Aberration Monitor for Optical Lithography” Peter Dirksen et al.; and the phase shift grating concept described in Optical Review No. 8 Vol. 4 (2001) p. 227-234 “Measurement of Wavefront Aberrations in Lithographic Lenses with an Optical Inspection Tool,” Hiroshi Nomura. In each case the output of the analysis tool are typically provided in terms of Zernike polynomial coefficients, which can accurately describe the induced phase error across the exit pupil of the lithographic lens in a form which can be easily interpreted in optically meaningful terms such as spherical, astigmatic and coma aberrations.
Although these aberration descriptors are generally accepted as quantitative metrics for the quality of lens systems, it is a non-trivial problem to quantitatively estimate the impact they will have on overlay, or more specifically the pattern placement error. Such calculations require detailed knowledge of other process parameters such as the exposure tool illumination configuration, wavelength, numerical aperture and the geometry of the pattern. In conventional overlay metrology using box in box targets as is common today, the impact of the exposure tool's optical aberrations on the accuracy of the metrology and the proper use of these metrology results for the purpose of overlay control is not taken into account at all.
Traditional overlay targets are characterized by large open areas and large feature sizes, which is very different than the transistors that they are trying to represent. Today's semiconductor processes are designed to optimize the transistors and circuitry feature sizes and pitches only. Therefore traditional overlay marks are not sensitive to the same aberrations as the transistors.
There have been recent disclosures, however, which attempt to deal with this issue by making box in box targets, which are more device representing (or device like) and process-robust. For ease of discussion “device representing” targets may be defined as a target that is sensitive to the same aberrations as a particular size and pitch of the transistor. Large open spaces are also subject to the adverse effects of other process areas (besides lithography), such as CMP polish and deposition. Further, “process-robust” targets may be defined as targets that are not adversely affected by these spurious processes. It should be noted that these two terms are defined in greater detail in the description of the invention.
By way of example, the “Box in Box” target has been modified to form a “Box in Bar” target and the “Bar in Bar” target. Both of these targets have the same general appearance as the “Box in Box” target. In “Box in Bar” targets, the outer box of the “Box in Box” target is separated into a plurality of parallel bars. In “Bar in Bar” targets, both the outer and inner box of the “Box in Box” target are separated into a plurality of parallel bars. More recently, there has been the introduction of separated bars that created features comparable to the design rules of the integrated circuit. See for example U.S. Patent Publication 2001 0055720 by Sato et al. While this method shows some potential in reducing the discrepancy between box in box scribeline structures and the overlay at the device structure itself, it still suffers from several short comings.
For one, the targets are typically limited in number and to specific places on the wafer and therefore they cannot compensate for the fact that the aberrations of the lithography tool vary across the exposure field. As should be appreciated, the available space on the wafer is severely restricted due to the fact that the real estate thereon is so expensive, i.e., most of the space on the wafer is reserved for dies. In most cases, the targets are spatially located in the scribeline at the perimeter of the exposure field, i.e., it is the space between the dies used for dicing the dies from the wafer. Furthermore, the number of targets in the scribeline is typically limited to four, one at each corner of the field. As should be appreciated, it is difficult to accurately determine how the overlay is behaving across the field (e.g. in the middle of the field) if only four places at the periphery of the field are sampled, i.e., if you only measure the four corners of the field, you have no knowledge of any other points. That is, overlay measurements carried at peripheral locations such as the scribeline do not necessarily represent the true overlay of the device features within the die since the aberrations of the lens vary across the exposure field of the lithography tool. By way of example, see SPIE vol. 3051 (1997) p. 362-373 “Minimization of Total Overlay Errors on Product Wafers Using an Advanced Optimization Scheme” Harry J. Levinson et al.
In addition, the targets are typically not optimized for the process and therefore the fine structures of the targets may suffer from process induced biases when measured by the metrology tool. As should be appreciated, each time a new process is introduced in microelectronic manufacture, there is some impact on the target. The ability to measure the target depends on it's visibility or contrast in the image acquisition microscope of the metrology tool. Some processes such as metallization by sputtering tend to diminish contrast, hence impacting precision. Other processes such as chemical mechanical polishing (CMP) tend to blur or distort the targets, hence impacting accuracy. These processes may also make the target features asymmetric or create an apparent spatial translation of the center of the target feature with respect to the center of the originally patterned trench or line.
Further, the box in box and related targets are asymmetric, i.e., the inner box is smaller and the outer box is bigger, and therefore each samples the optical metrology tool pupil differently. Further still, the box in box and related targets do not fully utilize the available scribeline space for metrology purposes. That is, they take up space due to the fact that they need to be spatially separated from one another in order to be correctly acquired by the overlay metrology tool, i.e., if not separated, the metrology tool runs the risk of measuring the wrong target. Moreover, the box in box and related targets are large and cumbersome compared to actual device being printed therewith, and therefore the correctables, which are based on the overlay measurements thereof, may not be the ideal correctables. For example, the correctables may indicate that a correction can be made to get the stepper aligned when ideally it would have been better to rework the wafer. Furthermore, because the overlay measurements are only performed at a few points on the wafer, the correctables may not facilitate optimal process control since they don't represent points across the field.
Other steps such as stepper matching have been utilized recently to reduce the impact of aberrations on wafer processing. Stepper matching generally refers to the process of determining which steppers work well together, i.e., matching steppers such that when two layers are printed on different steppers there is a minimum overlay error between the two layers. As should be appreciated, every stepper has its own unique signature of aberrations or other errors and therefore each stepper tends to print patterns differently for a given set of process conditions. The steppers that print patterns in a similar manner are matched thus minimizing the impact of these aberrations and other errors over the entire process. In most cases, stepper matching is performed by providing a golden wafer having a standard pattern; printing patterns on the golden wafer with each stepper using the same reticle and processing conditions; and calculating the relative difference between each of the steppers by comparing the alignment between the standard pattern and each of the stepper patterns. If the alignment between steppers is similar, then the steppers tend to work well together. If the alignment between steppers is different, then the steppers may not work well together. Although stepper matching provides some benefit, it is not ideal since it does not provide control feedback during wafer processing, i.e., it does not overcome the problems associated with conventional overlay targets and the manner in which the overlay error is determined therefrom.
In view of the foregoing, a method is desired which is able to isolate, quantify and/or minimize the impact of aberration effects and other process effects on overlay metrology. Furthermore, a method is desired that can utilize the overlay information in a scenario specific way to provide the most accurate possible feedback to the lithography cell for either lithography tool overlay control (e.g., correctables) or product lot dispositioning (e.g., rework).